1. Field of the Invention
This invention relates generally to the cell structure and fabrication process of semiconductor devices. More particularly, this invention relates to a novel and improved cell structure and improved process for fabricating a trenched semiconductor device, e.g., a trenched power MOSFET device, to eliminate gate oxide weak spot in a deep trench.
2. Description of the Prior Art
For those with ordinary skill in the art of semiconductor manufacture, there is still a technical difficulty in forming a thick oxide layer at the bottom of a trench opened in a semiconductor substrate. Specifically, in the process of forming a thick oxide layer at the bottom of a deep trench with a narrow trench critical dimension (CD), inevitably there are weak spots formed around the corners of the trench bottom. Particularly, these spots are developed at the points where the curvature of the surfaces of the insulator and silicon substrate meet. These weak spots are developed due to the restricted thermal Gate Oxide growth caused by the limited oxygen diffusion into the corner interface between insulator and sidewall substrate.
This technical difficulty often becomes a hindrance to implement a semiconductor device for high switching speed operation. Specifically, the switching speed is a strong function of the capacitance between the gate and the drain generally represented by Crss. In order to reduce the capacitance Crss to increase the switching speed a thick bottom oxide is deposited in the bottom of the trench. By depositing a thicker oxide layer at the bottom of the trench, the capacitance Crss can be reduced to two third or even smaller of the original capacitance without significantly impact to the on-resistance. However, due to the concern of the weak interface spots between the thick oxide bottom layer and the linen layer on the sidewalls, the reliability of semiconductor devices is adversely affected.
In U.S. Pat. No. 6,291,298, Williams et al. disclose a trench gate semiconductor device that has an increased thickness of the gate oxide at the bottom of the trench to diminish the high electric field at the corner of the trench. Different manufacturing processes are employed to increase the thickness of the trench bottom oxide layers. In U.S. Pat. Nos. 6,437,386, 6,573,569, and 6,709,930, several local oxidation of silicon (LOCOS) manufacturing processes are applied to deposit thick oxide layer at the bottom of a trench. However, the layer interfaces disposed near the corner of the trench bottom all have the weak spots that could develop into reliability problems during the life cycles of the device operation.
Referring to FIGS. 1A and 1B for a side cross sectional view and an explosive view respectively of a deep and narrow trench 10. At the bottom of the trench, there is a thick layer of oxide layer 15. The bottom corners 20 of the trench are located at the points where the curvatures of the surfaces of the trench bottom meet the thick oxide layer 15. At these interface points, the gate oxide layer growth is limited due to restricted oxygen diffusion into the corner interface. These weak points often leads to device reliability problems and may further adversely affect the device performance.
Therefore, there is still a need in the art of the semiconductor device fabrication, particularly for trenched power MOSFET design and fabrication, to provide a novel transistor structure and fabrication process that would resolve these difficulties and design limitations.